In aeronautics, onboard computers have to make numerous in-flight computations in order to perform control operations. For example the primary flight control computer carries out in-flight computations pertaining to autopilot flight control operations and the secondary flight control computer performs in-flight computations pertaining to control surface control operations. These control operations must be done regularly, at intervals of varying length and often in a particular order.
These control operations are called specifications. A specification in aeronautics is made by a set of logic boards used to describe functions. Each logic board has a set of logic elements (gates, latches etc.) as well as at least one input and one output enabling an electrical or logic link with the other boards that make the specification as well as with the logic boards of neighboring specifications.
Specifications require a large number of computations. Now, in aircraft, for reasons of space requirement and thermal dissipation, the onboard computers and especially the flight control computer cannot be very powerful, i.e. they cannot have very great computation capacity. The specifications therefore need to be managed so as to make the most efficient use of the computation capacities of the computer, known as CPU capacities. In other words, it is important that the specifications should be managed so as to spread out the computations in time, so that the processing operations for a specification do not all have to be performed simultaneously by the computer. It is therefore necessary to manage these processing operations so that they are distributed in time.
To this end, these specifications need to be sequenced, i.e. they need to be divided into sequences that can be ordered and distributed in time. The sequences can then be distributed among a predetermined number of processing tasks and executed at varying intervals.
Thus, each task has a predefined period and is divided into fixed number of sequences which shall also be called cycles. Each cycle is divided into sub-cycles whose number varies as a function of the period of execution of the cycle in relation to that of a task.
Each sequence of a specification is formed by processing operations called nodes which therefore have variable iteration rates defined by their cycle.
The nodes of a specification may have variable iteration frequencies depending on the importance of the node, the precision of the function desired, etc. For example, one node of a specification may necessitate an iteration rate of 10 ms while another node may necessitate a rate of 20 or 40 ms. The node iteration rate is therefore a first constraint on the specifications.
Certain nodes of a specification must be executed in a precise order. This precise order is a second constraint on the specifications.
The specifications may also have a hardware constraint, namely a constraint related to the inputs and outputs of the nodes. Indeed, the data transmitted from one node to another may accumulate in the form of queues at one output of a node. These outputs therefore need to be managed so as to prevent the formation of excessively long queues which the computer would be incapable of processing. These hardware constraints are a third type of constraint on specifications.
FIG. 1 shows an example of a specification comprising twelve processing tasks. Each task has a 10-ms time window, i.e. it can execute computations for a maximum duration of 10 ms. In example of FIG. 1, there are twelve tasks, each taking 10 ms. This set of twelve tasks is therefore reiterated every 120 ms. Each of these tasks comprises four basic cycles. The tasks, referenced task 1, task 2, . . . , task 12, each comprises four cycles C1, C2, C3 and C4. The cycles C1 to C4 have iteration rates that are different from one another. For example, the cycle C1 has a rate of 10 ms, C2 has a rate of 20 ms, C3 has a rate of 40 ms and C4 has a rate of 120 ms. The cycle C1 contains a sub-cycle. The cycle C2 contains two sub-cycles C21 and C22. It can thus be understood that the cycle C1 is reiterated in each of the tasks 1 to 12. By contrast, the cycle C2 has a two-task repetitiveness, i.e. it is executed in the task 1 then in the task 3, the task 5 etc. The sub-cycle of C2 executed in the tasks 1, 3, etc., is referenced C21. Similarly, the sub-cycle C22 is executed in the task 2 then repeated every 20 ms in the task 4, then the task 6, etc.
Each of the cycles enables a computation or a set of computations defined by nodes. Thus, the cycle C1 can execute a node A and a node B which will be repeated at the cycle C1 of each task 1 to 12. The sub-cycle C21 can execute the node C which will be reiterated at the tasks 3, 5, 7, etc. A node N, made in the sub-cycle C41 of the task 1, will be reiterated only at the task 1 of the next set of tasks. Thus, for example, between two iterations of the sub-cycle, in the task 1 and in the task 3, a sub-cycle C22 can execute different nodes, in task 2 and then in both tasks.
In this way, during a same time window, a node N is executed once in C4, while a node C is executed six times in C2. The division of the task into basic cycles having different occurrence rates makes it possible to modulate the repetitiveness of the different operations that have to be performed. This modulation of repetitiveness of the operations, and therefore of the nodes, is chosen as a function of the precision desired for operation, the importance of this operation or again the speed of reaction desired by the computer. The modulation of the refresh rate of the operations, as a function of the operations considered, thus improves the computation capacity of the computer.
At present, the sequencing of the flight control computer specifications is performed manually by operators. Indeed, in most classic aircraft, the number of nodes to be sequenced is in the range of 200 to 300. These nodes are distributed manually, by trial and error. The distribution of the nodes is therefore done according to the operator's knowledge and experience. The operator's competence alone provides for a sequencing that is more or less acceptable. Once the nodes have been distributed, the operator may, if necessary, modify this distribution of the nodes in the cycles in order to try and obtain improved balance in the tasks. However, given the complexity of the task, this has the effect of further extending the performance time of the sequencing without any certainty of improvement. It can be understood then that the sequencing of new specifications, which may comprise up to 3000 nodes, may necessitate several successive modifications on the part of the operator, i.e. several placing trials and therefore considerable time before the operator finds an acceptable sequencing.
At present, in certain aircraft, the computation capacity needed to perform the specifications is in the range of 60% to 70% of the maximum CPU load of the computer. Thus, by performing the sequencing of the specifications manually, an operator may obtain a sequencing enabling a free CPU load capacity of 30 to 40 percent. This free CPU load capacity is useful, especially to enable the addition of subsequent specifications as a function of the aircraft needs, even after the aircraft has been put into production. In other words, the operator seeks to obtain the most stable possible distribution so as to provide for the greatest possible margin of free CPU capacity. Thus, when stable sequencing is obtained, the operator may effect the validation of this sequencing and continue to develop, while keeping the already acquired sequencing without any need to revalidate the totality of the sequencing.
The CPU free load capacity is also used to provide a guarantee to the authorities that the maximum capacity of the computer will never be exceeded and that, therefore, there is no risk of a command not being executed in flight.
However, at present, aircraft builders are seeking to build ever bigger and ever more efficient aircraft to carry increasing quantities of goods and increasing numbers of passengers at lower cost but with improved comfort. With these new aircraft, the number of logic boards is increasing considerably as compared with a classic aircraft. The number of logic boards is in the range of the 2000 to 3000. It can therefore be understood that, with an operator working manually by a trial-and-error method, the sequencing of the specifications for 2000 to 3000 boards may take several days to perform. Furthermore, with this trial-and-error method, it is not certain that the operator will obtain an acceptable sequencing in the end.